Semiconductor device geometries have dramatically decreased in size since integrated circuits were first introduced several decades ago, and all indications are that this trend will continue on. Today's wafer fabrication plants are routinely producing devices having 0.25 μm and even 0.18 μm feature sizes, and the plants of the future will soon be producing devices having even smaller geometries.
As device sizes become smaller and integration density increases, one issue that has become an increasing concern to semiconductor manufacturers is that of inter-level “crosstalk.” Crosstalk is the undesired coupling of an electrical signal on one metal layer onto another metal layer, and arises when two or more layers of metal with intervening insulating or dielectric layers are formed on a substrate. Crosstalk can be reduced by moving the metal layers further apart, minimizing the areas of overlapping metal between metal layers, reducing the dielectric constant of the material between metal layers and combinations of these and other methods. Undesired coupling of electrical signals can also occur between adjacent conductive traces, or lines, within a conductive layer. As device geometries shrink, the conductive lines become closer together and it becomes more important to isolate them from each other.
Another issue that is becoming more of a concern with decreasing feature sizes is the “RC time constant ” of a particular trace. Each trace has a resistance, R, that is a product of its cross section and bulk resistivity, among other factors, and a capacitance, C, that is a product of the surface area of the trace and the dielectric constant of the material or the space surrounding the trace, among other factors. If a voltage is applied to one end of the conductive trace, charge does not immediately build up on the trace because of the RC time constant. Similarly, if a voltage is removed from a trace, the trace does not immediately drain to zero. Thus high RC time constants can slow down the operation of a circuit. Unfortunately, shrinking circuit geometries produce narrower traces, which results in higher resistivity. Therefore it is important to reduce the capacitance of the trace, such as by reducing the dielectric constant of the surrounding material between traces, to maintain or reduce the RC time constant.
Hence, in order to further reduce the size of devices on integrated circuits, it has become necessary to use insulators having a low dielectric constant. And as mentioned above, low dielectric constant films are particularly desirable for premetal dielectric (PMD) layers and intermetal dielectric (IMD) layers to reduce the RC time delay of the interconnect metallization, to prevent crosstalk between the different levels of metallization, and to reduce device power consumption.
The traditional insulator used in the fabrication of semiconductor devices has been undoped silicon oxide. Undoped silicon oxide films deposited using conventional CVD techniques may have a dielectric constant (k) as low as approximately 4.0 or 4.2. Many approaches have been proposed for obtaining insulating layers having a lower dielectric constant. Amongst these have been fluorine-doped silicon oxide films that may have a dielectric constant as low as 3.4 or 3.6. Another approach has been the development of carbon-doped silicon oxide (CDO) films. In some cases, CDO films are treated with e-beam radiation during and/or after growth in order to improve the film properties.
The use of electron beam (e-beam) radiation to treat materials is well known. For example, e-beams have been used for curing interlayer dielectrics for microelectronic devices, photoresist exposure, altering solubility characteristics of thin film layers, and the like. Often, the electron sources utilized in the past to generate e-beams for such electron beam treatments have been electron guns, which produce e-beams of narrow cross-section. For some applications, it is desirable to provide a large-area e-beam source which is controllable, uniform, insensitive to poor vacuum, and long lived. Thus, large area e-beam sources have been developed, some of which are suitable for use in semiconductor processing applications. An example of such a large-area e-beam source is described in U.S. Pat. No. 5,003,178, incorporated herein by reference in its entirety for all purposes.
When such a large area e-beam is used during a semiconductor fabrication process, charge buildup can occur in the materials present on the semiconductor substrate. For example, charge may buildup in dielectric layers deposited on the semiconductor substrate. Excessive charge buildup may result in unwanted electrical effects, including electrical breakdown across fragile structures such as MOS gate oxides, resulting in possible damage to the semiconductor devices.
Therefore, there is a need in the art for methods and structures which reduce the buildup of charge during electron beam treatment of semiconductor substrates.